1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to coherent multi-processing systems in which two or more processor cores share access to a coherent memory region.
2. Description of the Prior Art
It is known to provide coherent multi-processing systems in which two or more processor cores share access to a coherent memory region. Such systems are typically used to gain higher performance throughout the different processor cores executing respective data processing operations in parallel. Known data processing systems which provide such coherent multi-processing capabilities include IBM370 systems and SPARC multi-processing systems.
An important aspect of such coherent multi-processing systems is the need to co-ordinate the activity of the different processor cores and in particular manage the manner in which they access the coherent memory which they share. As an example, if one of the processor cores has read a data value from memory and is currently updating that data value prior to writing it back to memory, then an intervening action by another processor core seeking to read that same data value from the coherent shared memory needs to be provided with the updated data value even though this has not yet been written back to the main memory and is only present in one of the other processor cores. This type of situation requires coherency management and is one example of the type of coherent multi-processing management operations which can typically be provided by a memory access control unit within such a coherent multi-processing system. The memory access control unit is typically coupled to the processor cores by a memory bus carrying signals identifying desired memory transactions and signals characterising the state of the processor cores and required operations.